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Title: CAMAC-based interlock system for power-supply-hardware protection on MFTF

Conference ·
OSTI ID:6130078

This interlock module accepts 16 inputs and generates, in conjunction with an internal PROM map, 8 outputs. This decision process is autonomous of the CAMAC dataway and host computer. The map is generated, burned and verified by a user interactive program written to accept input/output equations in Boolean algebra. The interlock module requires the host computer to periodically interrogate it to verify proper operation of the module, host computer and date link; otherwise, permissives are dropped. An internal mask register may be used to override interlock inputs. This mask is perishable and must be constantly refreshed. Output drivers may be operated in a latch/no latch mode. This prevents outputs, once dropped, from being reasserted even if the proper input sequence is reestablished. A first-out register may be utilized to determine which input has dropped first in the event that chain reactions are developed among the interlock inputs.

Research Organization:
Lawrence Livermore National Lab., CA (USA)
DOE Contract Number:
W-7405-ENG-48
OSTI ID:
6130078
Report Number(s):
UCRL-86070; CONF-811040-25; ON: DE82001623; TRN: 82-001562
Resource Relation:
Conference: 9. symposium on engineering problems of fusion research, Chicago, IL, USA, 26 Oct 1981
Country of Publication:
United States
Language:
English