Fermilab Physics Department Fastbus TDC module

Conference · Mon Jul 01 00:00:00 EDT 1991

OSTI ID:5335199

Cancelo, G; Hansen, S; Cotta-Ramusino, A

A prototype 64 channel Fastbus TDC built at Fermilab is described. The module features a full custom CMOS four channel gated integrator chip. One level of analog buffering at the inputs is implemented on chip. A four event deep output queue at the bus interface allows a high event rate with low dead time. Each channel can record up to two hits per event. With an occupation rate of 10%, the module can operate at 40,000 events per second with dead time on the order of 15%. The TDC operates in common stop mode with a full scale of 1 {mu}sec and a resolution of 1 nsec. 5 refs., 6 figs.

• Research Organization: Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States)
• Sponsoring Organization: USDOE; USDOE, Washington, DC (United States)
• DOE Contract Number: AC02-76CH03000
• OSTI ID: 5335199
• Report Number(s): FNAL/C-91/189; CONF-9010220-30; ON: DE91016509
• Resource Relation: Conference: 1990 Institute of Electrical and Electronics Engineers (IEEE) nuclear science symposium, Arlington, VA (United States), 22-27 Oct 1990
• Country of Publication: United States
• Language: English

Related Subjects

43 PARTICLE ACCELERATORS
42 ENGINEERING
DATA ACQUISITION SYSTEMS
DESIGN
FASTBUS SYSTEM
CALIBRATION
FERMILAB ACCELERATOR
INTEGRATED CIRCUITS
MICROPROCESSORS
SWITCHING CIRCUITS
ACCELERATORS
COMPUTERS
CYCLIC ACCELERATORS
ELECTRONIC CIRCUITS
MICROELECTRONIC CIRCUITS
SYNCHROTRONS
430303* - Particle Accelerators- Experimental Facilities & Equipment
426000 - Engineering- Components
Electron Devices & Circuits- (1990-)