Constant fan-in digital neural networks are VLSI-optimal
The paper presents a theoretical proof revealing an intrinsic limitation of digital VLSI technology: its inability to cope with highly connected structures (e.g. neural networks). We are in fact able to prove that efficient digital VLSI implementations (known as VLSI-optimal when minimizing the AT{sup 2} complexity measure - A being the area of the chip, and T the delay for propagating the inputs to the outputs) of neural networks are achieved for small-constant fan-in gates. This result builds on quite recent ones dealing with a very close estimate of the area of neural networks when implemented by threshold gates, but it is also valid for classical Boolean gates. Limitations and open questions are presented in the conclusions.
- Research Organization:
- Los Alamos National Lab. (LANL), Los Alamos, NM (United States)
- Sponsoring Organization:
- USDOE Assistant Secretary for Human Resources and Administration, Washington, DC (United States)
- DOE Contract Number:
- W-7405-ENG-36
- OSTI ID:
- 486012
- Report Number(s):
- LA-UR-97-61; CONF-9507268-1; ON: DE97003400; TRN: 97:003923
- Resource Relation:
- Conference: Mathematics of neural networks and applications, Oxford (United Kingdom), 3-7 Jul 1995; Other Information: PBD: 1995
- Country of Publication:
- United States
- Language:
- English
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