Stresses from flip-chip assembly and underfill; measurements with the ATC4.1 assembly test chip and analysis by finite element method
The authors report the first measurements of in-situ flip-chip assembly mechanical stresses using a CMOS piezoresistive test chip repatterned with a fine pitch full area array. A special printed circuit board substrate was designed at Sandia and fabricated by the Hadco Corp. The flip-chip solder attach (FCA) and underfill was performed by a SEMATECH member company. The measured incremental stresses produced by the underfill are reported and discussed for several underfill materials used in this experiment. A FEM of a one-quarter section of the square assembly has been developed to compare with the measured as-assembled and underfill die surface stresses. The initial model utilized linear elastic constitutive models for the Si, solder, underfill, and PC board components. Detailed comparisons between theory and experiment are presented and discussed.
- Research Organization:
- Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
- Sponsoring Organization:
- USDOE Office of Financial Management and Controller, Washington, DC (United States)
- DOE Contract Number:
- AC04-94AL85000
- OSTI ID:
- 463650
- Report Number(s):
- SAND-96-2616C; CONF-970569-2; ON: DE97003842; TRN: AHC29709%%87
- Resource Relation:
- Conference: 47. electronic components and technology conference, San Jose, CA (United States), 18-21 May 1997; Other Information: PBD: [1996]
- Country of Publication:
- United States
- Language:
- English
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