System-wide power management control via clock distribution network

Coteus, Paul W.; Gara, Alan; Gooding, Thomas M.; Haring, Rudolf A.; Kopcsay, Gerard V.; Liebsch, Thomas A.; Reed, Don D.

Title: System-wide power management control via clock distribution network

Patent · Tue May 19 00:00:00 EDT 2015

OSTI ID:1179790

Coteus, Paul W.; Gara, Alan; Gooding, Thomas M.; Haring, Rudolf A.; Kopcsay, Gerard V.; Liebsch, Thomas A.; Reed, Don D.

An apparatus, method and computer program product for automatically controlling power dissipation of a parallel computing system that includes a plurality of processors. A computing device issues a command to the parallel computing system. A clock pulse-width modulator encodes the command in a system clock signal to be distributed to the plurality of processors. The plurality of processors in the parallel computing system receive the system clock signal including the encoded command, and adjusts power dissipation according to the encoded command.

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Research Organization:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Organization:: USDOE

DOE Contract Number:: B554331

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Number(s):: 9,037,892

Application Number:: 13/085,879

OSTI ID:: 1179790

Resource Relation:: Patent File Date: 2011 Apr 13

Country of Publication:: United States

Language:: English

References (12)

Power reduction of chip multi-processors using shared resource control cooperating with DVFS Watanabe, Ryo; Kondo, Masaaki; Nakamura, Hiroshi 2007 25th International Conference on Computer Design ICCD 2007 https://doi.org/10.1109/ICCD.2007.4601961	conference	October 2007
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Minimizing execution time in MPI programs on an energy-constrained, power-scalable cluster Springer, Robert; Lowenthal, David K.; Rountree, Barry Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming - PPoPP '06 https://doi.org/10.1145/1122971.1123006	conference	January 2006
The Implementation and Design of a Low-Power Clock Distribution Microarchitecture Ji, Rong; Zeng, Xianjun; Chen, Liang 2007 International Conference on Networking, Architecture, and Storage (NAS 2007) https://doi.org/10.1109/NAS.2007.54	conference	July 2007
Multiprocessor system with reduced power mode and improved variation of power demand Hara, Tsutomu; Maruyama, Takashi; Yoshidome, Hitoshi https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5724591 US Patent Document 5,724,591	patent	March 1998
System for reducing the power consumption of a computer system and method therefor Evoy, David R. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5787294 US Patent Document 5,787,294	patent	July 1998
System and method for phase-synchronous, flexible-frequency clocking and messaging Baxter, Michael A. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5805871 US Patent Document 5,805,871	patent	September 1998
Method and system for dynamically adjusting power consumption of an information handling system Lippert, Kurt J.; Fredlund, Loren; Vecera, Nathan https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7017061 US Patent Document 7,017,061	patent	March 2006
Multi-level power monitoring, filtering and throttling at local blocks and globally Choquette, Jack H.; Normoyle, Kevin; Atmeh, Elias https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7337339 US Patent Document 7,337,339	patent	February 2008
Apparatus and method for controlling power, clock, and reset during test and debug procedures for a plurality of processor/cores McGowan, Robert A. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7536597 US Patent Document 7,536,597	patent	May 2009
Power monitoring for processor module Schumacher, Derek; Martinez, Idis Ramona https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7613935 US Patent Document 7,613,935	patent	November 2009
Integrated circuit and signal processing apparatus using the same Kiyozaki, Kenichi https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7664973 US Patent Document 7,664,973	patent	February 2010

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