A Pixel Readout Chip in 40 nm CMOS Process for High Count Rate Imaging Systems with Minimization of Charge Sharing Effects
Abstract
We present a prototype chip in 40 nm CMOS technology for readout of hybrid pixel detector. The prototype chip has a matrix of 18x24 pixels with a pixel pitch of 100 μm. It can operate both in single photon counting (SPC) mode and in C8P1 mode. In SPC the measured ENC is 84 e₋rms (for the peaking time of 48 ns), while the effective offset spread is below 2 mV rms. In the C8P1 mode the chip reconstructs full charge deposited in the detector, even in the case of charge sharing, and it identifies a pixel with the largest charge deposition. The chip architecture and preliminary measurements are reported.
- Authors:
- Publication Date:
- Research Org.:
- Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States)
- Sponsoring Org.:
- USDOE Office of Science (SC), High Energy Physics (HEP)
- Contributing Org.:
- Pixels Collaboration
- OSTI Identifier:
- 1151753
- Report Number(s):
- FERMILAB-PUB-13-518-PPD
- DOE Contract Number:
- AC02-07CH11359
- Resource Type:
- Conference
- Journal Name:
- NSS/MIC 2013 Proceedings
- Additional Journal Information:
- Journal Volume: C13-10-26; Conference: 2013 IEEE Nuclear Science Symposium and Medical Imaging Conference, Seoul, (South Korea), 27 Oct - 02 Nov 2013
- Country of Publication:
- United States
- Language:
- English
- Subject:
- Rad Hard Vertex Detector
Citation Formats
Maj, Piotr, Grybos, P., Szczgiel, R., Kmon, P., Drozd, A., and Deptuch, G. A Pixel Readout Chip in 40 nm CMOS Process for High Count Rate Imaging Systems with Minimization of Charge Sharing Effects. United States: N. p., 2013.
Web. doi:10.1109/NSSMIC.2013.6829433.
Maj, Piotr, Grybos, P., Szczgiel, R., Kmon, P., Drozd, A., & Deptuch, G. A Pixel Readout Chip in 40 nm CMOS Process for High Count Rate Imaging Systems with Minimization of Charge Sharing Effects. United States. https://doi.org/10.1109/NSSMIC.2013.6829433
Maj, Piotr, Grybos, P., Szczgiel, R., Kmon, P., Drozd, A., and Deptuch, G. 2013.
"A Pixel Readout Chip in 40 nm CMOS Process for High Count Rate Imaging Systems with Minimization of Charge Sharing Effects". United States. https://doi.org/10.1109/NSSMIC.2013.6829433. https://www.osti.gov/servlets/purl/1151753.
@article{osti_1151753,
title = {A Pixel Readout Chip in 40 nm CMOS Process for High Count Rate Imaging Systems with Minimization of Charge Sharing Effects},
author = {Maj, Piotr and Grybos, P. and Szczgiel, R. and Kmon, P. and Drozd, A. and Deptuch, G.},
abstractNote = {We present a prototype chip in 40 nm CMOS technology for readout of hybrid pixel detector. The prototype chip has a matrix of 18x24 pixels with a pixel pitch of 100 μm. It can operate both in single photon counting (SPC) mode and in C8P1 mode. In SPC the measured ENC is 84 e₋rms (for the peaking time of 48 ns), while the effective offset spread is below 2 mV rms. In the C8P1 mode the chip reconstructs full charge deposited in the detector, even in the case of charge sharing, and it identifies a pixel with the largest charge deposition. The chip architecture and preliminary measurements are reported.},
doi = {10.1109/NSSMIC.2013.6829433},
url = {https://www.osti.gov/biblio/1151753},
journal = {NSS/MIC 2013 Proceedings},
number = ,
volume = C13-10-26,
place = {United States},
year = {Thu Nov 07 00:00:00 EST 2013},
month = {Thu Nov 07 00:00:00 EST 2013}
}
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