Low latency, high bandwidth data communications between compute nodes in a parallel computer

Blocksome, Michael A

Title: Low latency, high bandwidth data communications between compute nodes in a parallel computer

Patent · Tue Apr 01 00:00:00 EDT 2014

OSTI ID:1129091

Blocksome, Michael A

Methods, systems, and products are disclosed for data transfers between nodes in a parallel computer that include: receiving, by an origin DMA on an origin node, a buffer identifier for a buffer containing data for transfer to a target node; sending, by the origin DMA to the target node, a RTS message; transferring, by the origin DMA, a data portion to the target node using a memory FIFO operation that specifies one end of the buffer from which to begin transferring the data; receiving, by the origin DMA, an acknowledgement of the RTS message from the target node; and transferring, by the origin DMA in response to receiving the acknowledgement, any remaining data portion to the target node using a direct put operation that specifies the other end of the buffer from which to begin transferring the data, including initiating the direct put operation without invoking an origin processing core.

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Research Organization:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Organization:: USDOE

DOE Contract Number:: B554331

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Number(s):: 8,694,595

Application Number:: 13/671,055

OSTI ID:: 1129091

Resource Relation:: Patent File Date: 2012 Nov 07

Country of Publication:: United States

Language:: English

References (51)

I/O control system using buffer full/empty and zero words signals to control DMA read/write commands Sera, Akihiro; Goukon, Kazuhiko; Shibata, Yuji https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/4933840 US Patent Document 4,933,840	patent	June 1990
Congestion free packet network Golestani, S. Jamaloddin https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5050162 US Patent Document 5,050,162	patent	September 1991
Bulk-synchronous parallel computer Valiant, Leslie G. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5083265 US Patent Document 5,083,265	patent	January 1992
Message passing system for distributed shared memory multiprocessor system and message passing method using the same Yamada, Shigeki; Maruyama, Katsumi; Kubota, Minoru https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5617537 US Patent Document 5,617,537	patent	April 1997
Static routing system Hashimoto, Akira; Tamiya, Hirokazu https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5680116 US Patent Document 5,680,116	patent	October 1997
Barrier and eureka synchronization architecture for multiprocessors Kessler, Richard E.; Oberlin, Steven M.; Thorson, Gregory Michael https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5721921 US Patent Document 5,721,921	patent	February 1998
Parallel process scheduling method in a parallel computer and a processing apparatus for a parallel computer Ueno, Haruhiko https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5781775 US Patent Document 5,781,775	patent	July 1998
Message-passing multiprocessor system Moh, Sang Man; Shin, Sang Seok; Yoon, Suk Han https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5790530 US Patent Document 5,790,530	patent	August 1998
Parallel computer system with communications network for selecting computer nodes for barrier synchronization Horie, Takeshi; Nagatsuka, Masaaki; Kobayashi, Kenichi https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5928351 US Patent Document 5,928,351	patent	July 1999
Multi-tasking adapter for parallel network applications Feeney, James William; Olnowich, Howard Thomas; Wilhelm, Jr., George William https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6072781 US Patent Document 6,072,781	patent	June 2000
Seralized race-free virtual barrier network Thorson, Greg; Passint, Randal S.; Scott, Steven L. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6085303 US Patent Document 6,085,303	patent	July 2000
I/O protocol for highly configurable multi-node processing system Muller, P. Keith; Chow, Kit M. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6105122 US Patent Document 6,105,122	patent	August 2000
Apparatus and method for responding to a interruption of a packet flow to a high level data link controller in a signal processing system Iyer, Ramesh; Nguyen, Henry; Smith, Patrick J. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7054958 US Patent Document 7,054,958	patent	May 2006
Tables with direct memory access descriptor lists for distributed direct memory access Ganapathy, Kumar; Kanapathippillai, Ruban; Shah, Saurin https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7155541 US Patent Document 7,155,541	patent	December 2006
Chaining direct memory access data transfer operations for compute nodes in a parallel computer Archer, Charles J.; Blocksome, Michael A. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7805546 US Patent Document 7,805,546	patent	September 2010
Low latency, high bandwidth data communications between compute nodes in a parallel computer Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7827024 US Patent Document 7,827,024	patent	November 2010
Message communications of particular message types between compute nodes using DMA shadow buffers Blocksome, Michael A.; Parker, Jeffrey J. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7836143 US Patent Document 7,836,143	patent	November 2010
DMA controller and method for checking address of data to be transferred with DMA Shih, Chien-Yi https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20030233497 US Patent Application 10/443377; 20030233497	patent-application	December 2003
Method for performing DMA transfers with dynamic descriptor structure Lu, Ho-Keng; Chang, Chia-Ming; Lee, Tsai-Pao https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20050114561 US Patent Application 10/720403; 20050114561	patent-application	May 2005
Lightweight input/output protocol Mohamed, Ahmed H.; Voellm, Anthony F. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20050198113 US Patent Application 10/749959; 20050198113	patent-application	September 2005
Failover mechanisms in RDMA operations Blackmore, Robert S.; Chang, Fu Chung; Chaudhary, Piyush https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20060045005 US Patent Application 11/017574; 20060045005	patent-application	March 2006
Early interrupt notification in RDMA and in DMA operations Blackmore, Robert S.; Helmer, JR., Leonard W.; Heywood, Patricia E. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20060045109 US Patent Application 11/017573; 20060045109	patent-application	March 2006
RDMA server (OSI) global TCE tables Blackmore, Robert S.; Chaudhary, Piyush; Goscinski, Jason E. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20060047771 US Patent Application 11/017456; 20060047771	patent-application	March 2006
Interface internet protocol fragmentation of large broadcast packets in an environment with an unaccommodating maximum transfer unit Chang, Fu Chung; Chaudhary, Piyush; Doxtader, Jennifer M. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20060056405 US Patent Application 10/981097; 20060056405	patent-application	March 2006
Remote direct memory access system and method Gildea, Kevin J.; Govindaraju, Rama K.; Grice, Donald G. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20060075057 US Patent Application 10/929943; 20060075057	patent-application	April 2006
Memory-controller-embedded apparatus and procedure for achieving system-directed checkpointing without operating-system kernel support Stiffler, Jack J.; Burn, Donald D. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20060150010 US Patent Application 11/301814; 20060150010	patent-application	July 2006
Host buffer queues Beckett, Jeffrey Scott; Duckman, David James; Nicolson, IV, Alexander https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20060161733 US Patent Application 11/039446; 20060161733	patent-application	July 2006
Concurrency technique for shared objects Martin, Paul A.; Detlefs, David L.; Garthwaite, Alexander T. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20060161737 US Patent Application 11/384627; 20060161737	patent-application	July 2006
DMA engine for protocol processing Alexander, Thomas; Quattromani, Marc Alan; Rekow, Alexander https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20060206635 US Patent Application 11/373858; 20060206635	patent-application	September 2006
Virtualization for device sharing Torudbakken, Ola; Johnsen, Bjorn Dag https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20060253619 US Patent Application 11/291264; 20060253619	patent-application	November 2006
Packet transferring/transmitting method and mobile communication system Tomita, Tetsuo; Ikeda, Eiji; Kobayashi, Kazunari https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20080101295 US Patent Application 12/003283; 20080101295	patent-application	May 2008
RDMA systems and methods for sending commands from a source node to a target node for local execution of commands at the target node Leonard, Judson S.; Stewart, Lawrence C.; Gingold, David https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20080109573 US Patent Application 11/594443; 20080109573	patent-application	May 2008
Data Flow Control Within and Between DMA Channels Go, Dominic; Hayter, Mark D.; Kumar, Puneet https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20080222317 US Patent Application 11/682051; 20080222317	patent-application	September 2008
Remote Direct Memory Access Archer, Charles J>; Blocksome, Michael A. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20080267066 US Patent Application 11/740361; 20080267066	patent-application	October 2008
Message Communications of Particular Message Types Between Compute Nodes Using DMA Shadow Buffers Blacksome, Michael A.; Parker, Jeffrey J. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20080270563 US Patent Application 11/739948; 20080270563	patent-application	October 2008
Low Latency, High Bandwidth Data Communications Between Compute Nodes in a Parallel Computer Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20080281997 US Patent Application 11/746333; 20080281997	patent-application	November 2008
Controlling Data Transfers from an Origin Compute Node to a Target Compute Node Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20080301704 US Patent Application 11/754765; 20080301704	patent-application	December 2008
Data Communications Archer, Charles J.; Blocksome, Michael A.; Ratterman, JOseph D. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20080313341 US Patent Application 11/764302; 20080313341	patent-application	December 2008
Ultrascalable Petaflop Parallel Supercomputer Blumrich, Matthias A.; Chen, Dong; Chiu, George https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20090006808 US Patent Document 11/768905; 20090006808	patent-application	January 2009
Low Latency, High Bandwidth Data Communications Between Compute Nodes in a Parallel Computer Blocksome, Michael A. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20090019190 US Patent Application 11/776718; 20090019190	patent-application	January 2009
Pacing a Data Transfer Operation Between Compute Nodes on a Parallel Computer Blockstone, Michael A. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20090022156 US Patent Application 11/776707; 20090022156	patent-application	January 2009
Repeating Direct Memory Access Data Transfer Operations for Compute Nodes in a Parallel Computer Archer, Charles J.; Blocksome, Michael A. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20090031001 US Patent Application 11/829334; 20090031001	patent-application	January 2009
Self-Pacing Direct Memory Access Data Transfer Operations for Compute Nodes in a Parallel Computer Blocksome, Michael A. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20090031002 US Patent Application 11/829339; 20090031002	patent-application	January 2009
Chaining Direct Memory Access Data Transfer Operations for Compute Nodes in a Parallel Computer Archer, Charles J.; Blocksome, Michael A. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20090031055	patent-application	January 2009
Tracking Network Contention Archer, Charles J.; Peters, Amanda; Smith, Brian E. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20090154486 US Patent Application 11/955474; 20090154486	patent-application	June 2009
Determining A Path For Network Traffic Between Nodes In A Parallel Computer Archer, Charles J.; Peters, Amanda; Smith, Brian E. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20090248894 US Patent Application 12/060508; 20090248894	patent-application	October 2009
Determining A Path For Network Traffic Between Nodes In A Parallel Computer Archer, Charles J.; Peters, Amanda; Smith, Brian E. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20090248895 US Patent Application 12/060531; 20090248895	patent-application	October 2009
Replenishing Data Descriptors in a DMA Injection FIFO Buffer Archer, Charles J.; Blocksome, Michael A.; Cernohous, Bob R. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20100268852 US Patent Application 11/755501; 20100268852	patent-application	October 2010
Processing data communications messages with input/output control blocks Archer, Charles J.; Ricard, Gary R.; Smith, Brian E. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20110197204 US Patent Application 12/702661; 20110197204	patent-application	August 2011
Data Communications in a Parallel Active Messaging Interface of a Parallel Computer Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20120137294 US Patent Application 12/956903; 20120137294	patent-application	May 2012
Performing Collective Operations In A Distributed Processing System Archer, Charles J.; Carey, James E.; Markland, Matthew W. https://doi.org/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20130018947 US Patent Application 13/181601; 20130018947	patent-application	January 2013

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