Simplifying and speeding the management of intra-node cache coherence

Patent · Tue Apr 17 00:00:00 EDT 2012

OSTI ID:1040782

Blumrich, Matthias A ^[1]; Chen, Dong ^[2]; Coteus, Paul W ^[3]; Gara, Alan G ^[4]; Giampapa, Mark E ^[5]; Heidelberger, Phillip ^[6]; Hoenicke, Dirk ^[7]; Ohmacht, Martin ^[3]

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1. Ridgefield, CT
2. Croton on Hudson, NY
3. Yorktown Heights, NY
4. Mount Kisco, NY
5. Irvington, NY
6. Cortlandt Manor, NY
7. Ossining, NY

A method and apparatus for managing coherence between two processors of a two processor node of a multi-processor computer system. Generally the present invention relates to a software algorithm that simplifies and significantly speeds the management of cache coherence in a message passing parallel computer, and to hardware apparatus that assists this cache coherence algorithm. The software algorithm uses the opening and closing of put/get windows to coordinate the activated required to achieve cache coherence. The hardware apparatus may be an extension to the hardware address decode, that creates, in the physical memory address space of the node, an area of virtual memory that (a) does not actually exist, and (b) is therefore able to respond instantly to read and write requests from the processing elements.

• Research Organization: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
• Sponsoring Organization: USDOE
• DOE Contract Number: W-7405-ENG-48
• Assignee: International Business Machines Corporation (Armonk, NY)
• Patent Number(s): 8,161,248
• Application Number: 12/953,770
• OSTI ID: 1040782
• Country of Publication: United States
• Language: English

Related Subjects

97 MATHEMATICS AND COMPUTING