D0 Silicon Upgrade: Thermally Induced Stresses in the Components of a D0 Ladder in the Silicon Tracker
During the operation of the silicon tracker, the ladders will be in direct thermal contact with a cooling channel. The expected operating temperature of the cooling channel is 0 C, maintained by a cooling fluid whose bulk temperature is below 0 C. The assembly temperature is assumed to be 22 C. Due to the mis-match of material expansion coefficients, thermal stresses will be induced in the epoxy, beryllium, and silicon of the ladders. Calculations are presented here as well as some thermal cycling results on test samples. Shown in Figures 1 and 2 are perspective views of the top and bottom of a 3 chip ladder. The silicon temperature within the ladders will not be uniform due to the relative location of the heat dissipating components and the cooling channel. As an example the following plot demonstrates the expected temperature distribution in the 3 chip single sided ladder during operation. Under expected operating conditions of 0.75 W hybrid component power dissipation and 0.5 W per SVX II chip, the temperature profile is shown for two situations of how the ladder is constructed. The cooling channel corresponds roughly to locations on the silicon between 32 and 42 mm. The silicon in this region is sandwiched between two plates of beryllium and is about 4 C. For a construction temperature of 22 C the beryllium/silicon/beryllium assembly will see a 18 C change in temperature. To be conservative a 20 C temperature change will be assumed (some larger temperature extremes will be considered) within the ladder.
- Research Organization:
- Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States)
- Sponsoring Organization:
- USDOE Office of Science (SC)
- DOE Contract Number:
- AC02-07CH11359
- OSTI ID:
- 1033277
- Report Number(s):
- FERMILAB-D0-EN-454; TRN: US1200354
- Country of Publication:
- United States
- Language:
- English
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