The SPi chip as an integrated power management device for serial powering of future HEP experiments
Serial powering is one viable and very efficient way to distribute power to future high energy physics (HEP) experiments. One promising way to realize serial powering is to have a power management device on the module level that provides the necessary voltage levels and features monitoring functionality. The SPi (Serial Powering Interface) chip is such a power manager and is designed to meet the requirements imposed by current SLHC upgrade plans. It incorporates a programmable shunt regulator, two linear regulators, current mode ADCs to monitor the current distribution on the module, over-current detection, and also provides module power-down capabilities. Compared to serially powered setups that use discrete components, the SPi offers a higher level of functionality in much less real estate and is designed to be radiation tolerant. Bump bonding techniques are used for chip on board assembly providing the most reliable connection at lowest impedance. This paper gives an overview of the SPi and outlines the main building blocks of the chip. First stand alone tests are presented showing that the chip is ready for operation in serially powered setups.
- Research Organization:
- Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- AC02-07CH11359
- OSTI ID:
- 1001391
- Report Number(s):
- FERMILAB-CONF-10-523-PPD; TRN: US1100356
- Journal Information:
- PoS VERTEX2009:030,2009, Conference: Prepared for 18th Workshop on VERTEX 2009, Veluwe, The Netherlands, 13-18 Sep 2009
- Country of Publication:
- United States
- Language:
- English
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