Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors

Conference · Sat Sep 12 00:00:00 EDT 2009

DOI:https://doi.org/10.1109/PACT.2009.36· OSTI ID:986720

Lu, Qingda; Alias, Christophe; Bondhugula, Uday; Henretty, Thomas; Krishnamoorthy, Sriram; Ramanujam, J; Rountev, Atanas; Sadayappan, Ponnuswamy; Chen, Yongjian; Lin, Haibo; Ngai, Tin-Fook

With increasing numbers of cores, future CMPs (Chip Multi-Processors) are likely to have a tiled architecture with a portion of shared L2 cache on each tile and a bankinterleaved distribution of the address space. Although such an organization is effective for avoiding access hot-spots, it can cause a significant number of non-local L2 accesses for many commonly occurring regular data access patterns. In this paper we develop a compile-time framework for data locality optimization via data layout transformation. Using a polyhedral model, the program’s localizability is determined by analysis of its index set and array reference functions, followed by non-canonical data layout transformation to reduce non-local accesses for localizable computations. Simulation-based results on a 16-core 2D tiled CMP demonstrate the effectiveness of the approach. The developed program transformation technique is also useful in several other data layout transformation contexts.

• Research Organization: Pacific Northwest National Lab. (PNNL), Richland, WA (United States)
• Sponsoring Organization: USDOE
• DOE Contract Number: AC05-76RL01830
• OSTI ID: 986720
• Report Number(s): PNNL-SA-70540; KJ0402000; TRN: US201017%%491
• Resource Relation: Conference: The Eighteenth International Conference on Parallel Architectures and Compilation Techniques (PACT 2009)
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
COMPUTER ARCHITECTURE
ARRAY PROCESSORS
DISTRIBUTION
HOT SPOTS
OPTIMIZATION
TRANSFORMATIONS