Method and apparatus for in-system redundant array repair on integrated circuits

Patent · Tue Jul 29 00:00:00 EDT 2008

OSTI ID:984366

Bright, Arthur A ^[1]; Crumley, Paul G ^[2]; Dombrowa, Marc B ^[3]; Douskey, Steven M ^[4]; Haring, Rudolf A ^[5]; Oakland, Steven F ^[6]; Ouellette, Michael R ^[7]; Strissel, Scott A ^[8]

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1. Croton-on-Hudson, NY
2. Yorktown Heights, NY
3. Bronx, NY
4. Rochester, MN
5. Cortlandt Manor, NY
6. Colchester, VT
7. Westford, VT
8. Byron, MN

Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

• Research Organization: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
• Sponsoring Organization: USDOE
• DOE Contract Number: W-7405-ENG-48
• Assignee: International Business Machines Corporation (Armonk, NY)
• Patent Number(s): 7,405,990
• Application Number: 11/872,085
• OSTI ID: 984366
• Country of Publication: United States
• Language: English

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