A Modular Approach to Model Heterogeneous MPSoC at Cycle Level
This paper proposes a system-level cycle-based framework to model and design heterogeneous Multiprocessor Systems on-Chip (MPSoC), called GRAPES. The approach features flexibility and modularity maintaining high simulation speed despite modeling at cycle level. Intellectual Property (IP) system modules can be described as C++ or SystemC entities and they are wrapped into C++ objects, called plug-ins. Plug-ins, that are modeled by the Transaction Level Modeling (TLM) style, are managed by the GRAPES kernel, which is the core of the simulation framework. GRAPES structural approach permits to easily model run-time reconfiguration and power modeling. Furthermore, it has been used to model and to simulate a case study of a scalable and heterogeneous MPSoC based on Network-on-Chip (NoC) interconnect.
- Research Organization:
- Pacific Northwest National Lab. (PNNL), Richland, WA (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- AC05-76RL01830
- OSTI ID:
- 966010
- Report Number(s):
- PNNL-SA-60933; KJ0402000; TRN: US200921%%477
- Resource Relation:
- Conference: 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, (DSD '08), September 3-5, 2008, Parma, Italy, 158-164
- Country of Publication:
- United States
- Language:
- English
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