Implementation of an imprint damascene project for interconnectfabrication
Advanced integrated circuits require eight or more levels ofwiring to transmit electrical signal and poweramong devices and toexternal circuitry. Each wiring level connects to the levels above andbelow it through via layers. The dual damascene approach to fabricatingthese interconnected structures creates a wiring level and a via levelsimultaneously, thereby reducing the total number of processing steps.However, the dual damascene strategy (of which there are severalvariations) still requires around 20 process steps per wiring layer. Inthis work, an approach to damascene processing that is based onstep-and-flash imprint lithography (SFIL) is discussed. This imprintdamascene process requires fewer than half as many steps as the standardphotolithographic dual damascene approach. Through use of a template withtwo tiers of patterning, a single imprint lithography step can replacetwo photolithography steps. Further improvements in efficiency arepossible if the imprint material is itself a functional dielectricmaterial. This work is a demonstration of the compatibility of imprintlithography (specifically SFIL) with back-end-of-line processing using adual damascene approach with functional materials.
- Research Organization:
- Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States)
- Sponsoring Organization:
- USDOE Director. Office of Science. Biological andEnvironmental Research
- DOE Contract Number:
- DE-AC02-05CH11231
- OSTI ID:
- 918118
- Report Number(s):
- LBNL-61654; JVTBD9; R&D Project: 50MF40; TRN: US200817%%1132
- Journal Information:
- Journal of Vacuum Science&Technology B:Microelectronics and Nanometer Structures, Vol. 24, Issue 3; Related Information: Journal Publication Date: 05/01/2006; ISSN 0734-211X
- Country of Publication:
- United States
- Language:
- English
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