Electrochemical planarization for microelectronic circuits

Conference · Thu Mar 25 00:00:00 EST 1993

OSTI ID:7368525

Contolini, R J; Mayer, S T; Bernhardt, A F

The need for flatter and smoother surfaces (planarization) in microelectronic circuits increases as the number of metal levels in ultra large scale integrated (ULSI) circuits increases. At Lawrence Livermore National Laboratory, the authors have developed an electrochemical planarization process that fills vias and trenches with metal (without voids) and subsequently planarizes the surface. Use is made of plasma-enhanced chemical vapor deposition (PECVD) of SiO[sub 2] for the dielectric layers and electroplated copper for the metalization. This report describes the advantages of this process over existing techniques, possibilities for collaboration, and previous technology transfer.

• Research Organization: Lawrence Livermore National Lab., CA (United States)
• Sponsoring Organization: USDOE; USDOE, Washington, DC (United States)
• DOE Contract Number: W-7405-ENG-48
• OSTI ID: 7368525
• Report Number(s): UCRL-JC-113618; CONF-9303198-1; ON: DE93017214
• Resource Relation: Conference: National Center for Advanced Information Components Manufacturing (NCAICM) workshop, Albuquerque, NM (United States), 30-31 Mar 1993
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
MICROELECTRONIC CIRCUITS
ELECTROCHEMICAL MACHINING
SURFACE FINISHING
CHEMICAL VAPOR DEPOSITION
COPPER
COST
ELECTROPLATING
SILICON OXIDES
TECHNOLOGY TRANSFER
CHALCOGENIDES
CHEMICAL COATING
CHEMICAL MACHINING
DEPOSITION
ELECTRODEPOSITION
ELECTROLYSIS
ELECTRONIC CIRCUITS
ELEMENTS
LYSIS
MACHINING
METALS
OXIDES
OXYGEN COMPOUNDS
PLATING
SILICON COMPOUNDS
SURFACE COATING
TRANSITION ELEMENTS
426000* - Engineering- Components
Electron Devices & Circuits- (1990-)
420200 - Engineering- Facilities
Equipment
& Techniques