A virtual zero-time, monolithic systolic sorting array

Conference · Mon Jan 01 00:00:00 EST 1990

OSTI ID:7264121

Britton, Jr, C L; Ericson, M N; Bouldin, D W ^[1]

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1. Oak Ridge National Lab., TN (USA)

A virtual zero-time monolithic sorting chip is described. The chip has a systolic array architecture and implements the sinking sort'' algorithm. The basic functional module of the systolic array is detailed and development techniques employed as well as functional simulation and results are presented. Lessons learned and educational significance of the development of this chip at a university are discussed. 3 refs., 4 figs.

• Research Organization: Oak Ridge National Lab., TN (USA)
• Sponsoring Organization: DOE/ER
• DOE Contract Number: AC05-84OR21400
• OSTI ID: 7264121
• Report Number(s): CONF-900464-1; ON: DE90001000
• Resource Relation: Conference: IEEE Southeastcon, New Orleans, LA (USA), 1-4 Apr 1990
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
SORTING
COMPUTER ARCHITECTURE
ALGORITHMS
DATA PROCESSING
DESIGN
INTEGRATED CIRCUITS
PERSONAL COMPUTERS
TESTING
COMPUTERS
DIGITAL COMPUTERS
ELECTRONIC CIRCUITS
MATHEMATICAL LOGIC
MICROCOMPUTERS
MICROELECTRONIC CIRCUITS
PROCESSING
990200* - Mathematics & Computers