A BiCMOS time interval digitizer based on fully-differential, current-steering circuits
- Stanford Univ., CA (United States). Center for Integrated Systems
A time interval digitizer cell with a 0--16 ns input range and a nominal LSB width of 1.0 ns has been integrated in a 2-[mu]m BiCMOS technology. The circuit exhibits both integral and differential nonlinearity below 0.15 LSB and a timing error of 0.32 ns RMS. Logic gate propagation delays are used as time measurement units, and the nominal value of the delays is set by an on-chip phase-locked loop (PLL). Fully-differential, current-steering circuits with low voltage swings are used to implement the time interval digitizer so as to generate minimal switching noise. The cell is to be used in the monolithic, multi-channel realization of a high-sensitivity, mixed-signal data acquisition front-end. By virtue of the time digitization architecture used, the average power dissipation of the cell is only 19.8 mW, despite the use of circuits that dissipate static power, and the layout area is a compact 448 [mu]m x 634 [mu]m.
- DOE Contract Number:
- AC03-76SF00515
- OSTI ID:
- 7048309
- Journal Information:
- IEEE Journal of Solid-State Circuits (Institute of Electrical and Electronics Engineers); (United States), Vol. 29:6; ISSN 0018-9200
- Country of Publication:
- United States
- Language:
- English
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