A hardware accelerator for maze routing
Journal Article
·
· IEEE (Institute of Electrical and Electronics Engineers) Transactions on Computers; (USA)
- Gongneung Nowo-Gu, Seoul (KR)
- Minnesota Univ., Minneapolis, MN (USA). Dept. of Computer Science
- MCC, Austin, TX (US)
In this paper, the authors reexamine the problem of developing a suitable hardware accelerator for a maze router. The design is comprised of three 3-stage pipelines and a banked memory. The banked memory permits read/write to occur with no wait and no conflicts.
- OSTI ID:
- 6996216
- Journal Information:
- IEEE (Institute of Electrical and Electronics Engineers) Transactions on Computers; (USA), Vol. 39:1; ISSN 0018-9340
- Country of Publication:
- United States
- Language:
- English
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