Fault tolerance in a systolic residue arithmetic processor array

Journal Article · Fri Jul 01 00:00:00 EDT 1988 · IEEE Trans. Comput.; (United States)

DOI:https://doi.org/10.1109/12.2239· OSTI ID:6992967

Cosentino, R J

The technique described in this paper exploits the regularity of systolic arrays and the potential for redundancy in residue number systems to provide fault tolerance in VLSI systems. The fault tolerance is concurrent with normal circuit operations and allows a continuous flow of correct data when a fault occurs. There is no interruption of valid data flow while the circuits are reconfigured. The technique also obviates the need for ultrahigh-reliability switches and switching control circuits. A fault-tolerant implementation of a finite impulse response filter with five residue channels, two of which are redundant, demonstrate the technique. As long as not more than one cell in each processing block is faulty, the filter outputs contain no errors.

• Research Organization: The Mitre Corp., Bedford, MA (US)
• OSTI ID: 6992967
• Journal Information: IEEE Trans. Comput.; (United States), Vol. 37:7
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
ARRAY PROCESSORS
FAULT TOLERANT COMPUTERS
COMPUTER CALCULATIONS
DATA TRANSMISSION
INTEGRATED CIRCUITS
PARALLEL PROCESSING
COMMUNICATIONS
COMPUTERS
DIGITAL COMPUTERS
ELECTRONIC CIRCUITS
MICROELECTRONIC CIRCUITS
PROGRAMMING
990210* - Supercomputers- (1987-1989)