Defect detection and classification in VLSI pattern inspection
Inspection of VLSI circuit patterns is becoming increasingly important in maintaining high yields as the scale of integration in electronic circuits continues to increase. Most mask- and wafer-inspection systems compare a die image to the image derived from the design data base. In this approach, some form of alignment between the acquired image and reference data is required and the volume of the data base becomes enormous as die complexity increases; in addition, defects cannot be classified. Alternative approaches studied in this work detect and classify defects by employing the geometric properties of local images. In the first approach, a local image is compared to template sets representing both acceptable and defective patterns. In the second approach, relevant topological properties can be obtained by determining the Euler number and its derivatives. In the third approach, a new chain-coding scheme is developed from which the geometric properties can be obtained. Custom VLSI chips comprised of maskable content-addressable memories have been designed, fabricated, and tested as an implementation of a high-speed template-matching system.
- Research Organization:
- Stanford Univ., CA (USA)
- OSTI ID:
- 6984093
- Resource Relation:
- Other Information: Thesis (Ph. D.)
- Country of Publication:
- United States
- Language:
- English
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