The monarch parallel processor hardware design
- BBN Systems and Technologies Corp., Cambridge, MA (US)
The authors report on their development of the Monarch parallel processor. Today, the Monarch's design is largely done and well into implementation. The high-speed interconnection network has been tested with two-micron switch chips, logging more than 30,000 device hours of operation at 125 mega bits per second passing over 10{sup 16} bits. The processor's logic design is almost complete and simulated. The memory controller and concentrator remain to be designed. The authors have analyzed the software in detail with the use of hand-coded examples, a simulator, and a rudimentary compiler. The authors are currently seeking support to finish the implementation.
- OSTI ID:
- 6934610
- Journal Information:
- Computer; (USA), Vol. 23:4; ISSN 0018-9162
- Country of Publication:
- United States
- Language:
- English
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