Synchronizing large systolic arrays
Parallel computing structures consist of many processors operating simultaneously. If a concurrent structure is regular, as in the case of systolic array, it may be convenient to think of all processors as operating in lock step. Totally synchronized systems controlled by central clocks are difficult to implement because of the inevitable problem of clock skews and delays. An alternate means of enforcing necessary synchronization is the use of self-timed, asynchronous schemes, at the cost of increased design complexity and hardware cost. Realizing that different circumstances call for different synchronization methods, this paper provides a spectrum of synchronization models; based on the assumptions made for each model, theoretical lower bounds on clock skew are derived, and appropriate or best-possible synchronization schemes for systolic arrays are proposed. This paper represents a first step towards a systematic study of synchronization problems for large systolic arrays.
- Research Organization:
- Carnegie-Mellon Univ., Pittsburgh, PA (USA). Dept. of Computer Science
- OSTI ID:
- 6755566
- Report Number(s):
- AD-A-123374/1
- Country of Publication:
- United States
- Language:
- English
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