Vector computer memory bank contention

Journal Article · Sun Mar 01 00:00:00 EST 1987 · IEEE Trans. Comput.; (United States)

DOI:https://doi.org/10.1109/TC.1987.1676901· OSTI ID:6700795

Bailey, D H

A number of recent vector supercomputer designs have featured main memories with very large capacities, and presumably even larger memories are planned for future generations. While the memory chips used in these computers can store much larger amounts of data than before, their operation speeds are rather slow when compared to the significantly faster CPU (central processing unit) circuitry in new supercomputer designs. A consequence of this speed disparity between CPU's and main memory is that memory access times and memory bank reservation times (as measured in CPU ticks) are sharply increased from previous generations. While it has been recognized that these longer memory operation times will reduce scalar performance, it has not been generally realized that vector performance could suffer as well, due to a sharp increase in memory bank contention. This paper examines this phenomenon using both a Markov chain mathematical model and a Monte Carlo simulation program. The potential for performance reduction is described and techniques for ameliorating this reduction are proposed.

• Research Organization: Numerical Aerodynamic Simulation Systems Div., NASA Ames Research Center, Moffet Field, CA 94035
• OSTI ID: 6700795
• Journal Information: IEEE Trans. Comput.; (United States), Vol. C-36:3
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
MEMORY DEVICES
COMPUTERIZED SIMULATION
PERFORMANCE
SUPERCOMPUTERS
VECTOR PROCESSING
ARRAY PROCESSORS
COMPUTER CODES
INTEGRATED CIRCUITS
MARKOV PROCESS
MATHEMATICAL MODELS
MONTE CARLO METHOD
PLANNING
COMPUTERS
DIGITAL COMPUTERS
ELECTRONIC CIRCUITS
MICROELECTRONIC CIRCUITS
PROGRAMMING
SIMULATION
STOCHASTIC PROCESSES
990210* - Supercomputers- (1987-1989)