A VLSI structure for the deadlock avoidance problem
Journal Article
·
· J. Parallel Distrib. Comput.; (United States)
In this paper the authors present two VLSI structures implementing the banker's algorithm for the deadlock avoidance problem, and we derive the area x (time)/sup 2/ lower bound for such an algorithm. The first structure is based on the VLSI mesh of trees. The second structure is a modification of the first one, and it approaches more closely the theoretical lower bound.
- Research Organization:
- Istituto di Analisi dei Sistemi ed Informatica del CNR, Viale Manzoni 30, 00185 Rome
- OSTI ID:
- 6533943
- Journal Information:
- J. Parallel Distrib. Comput.; (United States), Vol. 2:4
- Country of Publication:
- United States
- Language:
- English
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99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
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