Two CMOS memory cells suitable for the design of SEU-tolerant VLSI circuits

Conference · Thu Dec 01 00:00:00 EST 1994 · IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States)

OSTI ID:6488567

Velazco, R; Bessot, D ^[1]; Duzellier, S ^[2]; Ecoffet, R ^[3]; Koga, R ^[4]

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1. Lab. de Genie Informatique LGI, Grenoble (France)
2. CERT-ONERA/DERTS, Toulouse (France)
3. CNES, Toulouse (France)
4. Aerospace Corp., Los Angeles, CA (United States)

Two new CMOS memory cells, called HIT cells, designed to be SEU-immune are presented. Compared to previously reported design hardened solutions, the HIT cells feature better electrical performances and consume less silicon area. SEU tests performed on a prototype chip prove the efficiency of the approach.

• OSTI ID: 6488567
• Report Number(s): CONF-940726-; CODEN: IETNAE
• Journal Information: IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States), Vol. 41:6Pt1; Conference: 31. annual international nuclear and space radiation effects conference, Tucson, AZ (United States), 18-22 Jul 1994; ISSN 0018-9499
• Country of Publication: United States
• Language: English

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