A multiple fault-tolerant processor network architecture for pipeline computing
Journal Article
·
· IEEE Trans. Comput.; (United States)
- Computer Center, Technical Univ. of Poznan, 60-965 Poznan (PL)
Certain fault-tolerant multiprocessor networks that can emulate linear array interconnections are considered. The system is fault tolerant of (m - 1) node and link failures. One of the particularly attractive features of this network is that it allows for a linear array structure starting with any node even in spite of (m - 2) faults. The configuration algorithm is fully distributed, and is performed on the basis of test results obtained from nonfaulty processors only. A simple fault identification procedure is developed using the above routing algorithm.
- OSTI ID:
- 6476452
- Journal Information:
- IEEE Trans. Comput.; (United States), Vol. 37:11
- Country of Publication:
- United States
- Language:
- English
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