A 256-element associative parallel processor

Journal Article · Sat Apr 01 00:00:00 EST 1995 · IEEE Journal of Solid-State Circuits

DOI:https://doi.org/10.1109/4.375954· OSTI ID:64609

Herrmann, F P; Sodini, C G ^[1]

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1. Massachusetts Institute of Technology, Cambridge, MA (United States). Dept. of Electrical Engineering

A 256-element associative processing chip is designed for pixel-parallel image processing and machine vision applications. A five-transistor three-state dynamic memory cell is used, and each processing element has 64 trits of memory. Other processing element components include a function generator, an activity register, and connections to a reconfigurable mesh network and a response resolution subsystem. These are implemented with compact circuits designed within memory pitch constraints. The chip was fabricated in a double-poly CCD-CMOS process and characterized as fully functional. A sample image processing application is demonstrated on a four-chip prototype system.

• OSTI ID: 64609
• Journal Information: IEEE Journal of Solid-State Circuits, Vol. 30, Issue 4; Other Information: PBD: Apr 1995
• Country of Publication: United States
• Language: English

Related Subjects

99 MATHEMATICS
COMPUTERS
INFORMATION SCIENCE
MANAGEMENT
LAW
MISCELLANEOUS
IMAGE PROCESSING
PARALLEL PROCESSING
COMPUTER ARCHITECTURE
MEMORY DEVICES
INTEGRATED CIRCUITS