skip to main content
OSTI.GOV title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Modeling and optimization of ultra high speed devices and circuits

Miscellaneous ·
OSTI ID:6147555

This thesis consists of two parts. In part one, we have developed an optimization scheme for designing submicron metal-oxide-semiconductor field effect transistors (MOSFETs). The scheme, which is based on the concepts of a mathematical programming problem, considers all the necessary performance and reliability issues and attempts to approach a desired set of target values. The modified pattern search method is used to implement the optimization scheme selected in this work. Simulated results have been compared with experimental data, and excellent agreement has been observed. Using the optimization scheme, a 0.6 {mu}m channel length MOSFET for possible dynamic random access memory (DRAM) applications has been designed. The other part of this thesis is devoted to the design of an ultra-fast 8 x 8-bit multiplier/accumulator circuit based on a resonant tunneling transistor (RTT) technology. The multiplier circuit has a parallel architecture and uses the carry save adder technique. The design of all the logic gates of the multiplier/accumulator circuit is based on the three logics: NAND, NOR, and NOT. The number of transistors applied in the RTT circuit is 2371, and the active chip area is about 0.30mm{sup 2}. The multiplier speed is 79 ps with an average power dissipation of 2.28 miliwatts (mW). The clock signals required for the operation of the chip are generated by a clock driver circuit which was designed by a ring oscillator and a binary counter circuit.

Research Organization:
Oklahoma Univ., Norman, OK (USA)
OSTI ID:
6147555
Resource Relation:
Other Information: Thesis (Ph. D.)
Country of Publication:
United States
Language:
English