Performance evaluation of vector-machine architectures
Vector machines are well known for their high-peak performance, but the delivered performance varies greatly over different workloads and depends strongly on compiler optimizations. Recently it has been claimed that several horizontal superscalar architectures, e.g., VLIW and polycyclic architectures, provide a more balanced performance across a wider range of scientific workloads than do vector machines. The purpose of this research is to study the performance of register-register vector processors, such as Cray supercomputers, as a function of their architectural features, scheduling schemes, compiler optimization capabilities, and program parameters. The results of this study also provide a base for comparing vector machines with horizontal superscalar machines. An evaluation methodology, based on timing parameters, bottle-necks, and run time bounds, is developed. Cray-1 performance is degraded by the multiple memory loads of index-misaligned vectors and the inability of the Cray Fortran Compiler (CFT) to produce code that hits all the chain slot times. The impact of chaining and two instruction scheduling schemes on one-memory-port vector supercomputers, illustrated by the Cray-1 and Cray-2, is studied. The lack of instruction chaining on the Cray-2 requires a different instruction scheduling scheme from that of the Cray-1. Situations are characterized in which simple vector scheduling can generate code that fully utilizes one functional unit for machines with chaining. Even without chaining, polycyclic scheduling guarantees full utilization of one functional unit, after an initial transient, for loops with acyclic dependence graphs.
- Research Organization:
- Illinois Univ., Urbana, IL (USA)
- OSTI ID:
- 6089413
- Resource Relation:
- Other Information: Thesis (Ph. D.)
- Country of Publication:
- United States
- Language:
- English
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Related Subjects
COMPUTER ARCHITECTURE
PERFORMANCE
CRAY COMPUTERS
VECTOR PROCESSING
EVALUATION
MEMORY MANAGEMENT
MODIFICATIONS
SUPERCOMPUTERS
TASK SCHEDULING
COMPUTERS
DATA PROCESSING
DIGITAL COMPUTERS
PROCESSING
PROGRAMMING
990200* - Mathematics & Computers