Modular architecture for high performance implementation of the FFT algorithm
- Department of Electrical Engineering, Technical University of Kielce, 25-314 Kielce (PL)
- ZWUT, Warsaw (PL)
This paper presents a new VLSI-oriented architecture to compute discrete Fourier transform. It consists of a homogeneous structure of processing elements. The structure has a performance equal to 1/{ital t} transforms per second, where {ital t} is the time needed for the execution of a single butterfly computation or the time needed for the collection of a complete vector of samples, whichever occurs to be longer. Although the system is not optimal (it achieves {ital O(N}{sup 3} log{sup 4} {ital N)} area time{sup 2} performance), the architecture is modular and makes it possible to design a system which performs FFT of any size without any extra circuitry. Moreover, the system can provide a built-in self-test and self-restructuring. The system consists of only one type of integrated circuit, its structure being irrespective of the transform size, which considerably reduces the cost of implementation.
- OSTI ID:
- 5903387
- Journal Information:
- IEEE Transactions on Computers (Institute of Electrical and Electronics Engineers); (USA), Vol. 39:12; ISSN 0018-9340
- Country of Publication:
- United States
- Language:
- English
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INTEGRATED CIRCUITS
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EFFICIENCY
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990200* - Mathematics & Computers