SEU-hardened silicon bipolar and GaAs MESFET SRAM cells using local redundancy techniques

Journal Article · Sat Feb 01 00:00:00 EST 1992 · IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States)

DOI:https://doi.org/10.1109/23.120128· OSTI ID:5694145

Hauser, J R ^[1]

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1. Dept. of Electrical and Computer Engineering, North Carolina State Univ., Raleigh, NC (US)

Silicon bipolar and GaAs FET SRAM's have proven to be more difficult to harden with respect to single-event upset mechanisms than have silicon CMOS SRAM's. This is a fundamental property of bipolar and JFET or MESFET device technologies which do not have a high-impedance, nonactive isolation between the control electrode and the current or voltage being controlled. All SEU circuit level hardening techniques applied at the local level must use some type of information storage redundancy so that information loss on one node due to an SEU event can be recovered from information stored elsewhere in the cell. In CMOS technologies, this can be achieved by the use of simple cross-coupling resistors, whereas in bipolar and FET technologies, no such simple approach is possible. Several approaches to the use of local redundancy in bipolar and FET technologies are discussed in this paper. At the expense of increased cell complexity and increased power consumption and write time, several approaches are capable of providing complete SEU hardness at the local cell level.

• OSTI ID: 5694145
• Journal Information: IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States), Vol. 39:1; ISSN 0018-9499
• Country of Publication: United States
• Language: English

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