High-speed parallel-processing networks for advanced architectures
This paper describes various parallel-processing architecture networks that are candidates for eventual airborne use. An attempt at projecting which type of network is suitable or optimum for specific metafunction or stand-alone applications is made. However, specific algorithms will need to be developed and bench marks executed before firm conclusions can be drawn. Also, a conceptual projection of how these processors can be built in small, flyable units through the use of wafer-scale integration is offered. The use of the PAVE PILLAR system architecture to provide system level support for these tightly coupled networks is described. The author concludes that: (1) extremely high processing speeds implemented in flyable hardware is possible through parallel-processing networks if development programs are pursued; (2) dramatic speed enhancements through parallel processing requires an excellent match between the algorithm and computer-network architecture; (3) matching several high speed parallel oriented algorithms across the aircraft system to a limited set of hardware modules may be the most cost-effective approach to achieving speed enhancements; and (4) software-development tools and improved operating systems will need to be developed to support efficient parallel-processor use.
- Research Organization:
- Air Force Avionics Lab., Wright-Patterson AFB, OH (USA)
- OSTI ID:
- 5626113
- Report Number(s):
- AD-P-005777/8/XAB
- Resource Relation:
- Other Information: This article is from 'Computing Systems Configuration for Highly Integrated Guidance and Control Systems.' AD-A199 308, 8.1-8.17; Availability: This paper covered by copyright. No copies furnished by DTIC/NTIS
- Country of Publication:
- United States
- Language:
- English
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