Hybrid wafer-scale processor. Final report, 15 July 1988-14 January 1989
The basic goal of this project is to develop and demonstrate techniques for the reduction of power consumption of space-based processors for infrared-surveillance systems. The primary technique is to minimize the capacitive loading encountered in off-chip communications for highly concurrent processing architectures. Both processing architecture and chip packaging are simultaneously considered to maximize MOPS per watt by increasing throughput while reducing system capacitance, signal delay, noise, voltage swing, and power consumption (the costs of system communications). With conventional packaging technology, highly concurrent processing architectures result in hardware implementations that are extremely large, very heavy, and that consume excessive power. Monolithic wafer-scale integration is theoretically ideal but requires an extensive amount of redundant circuitry and provisions for circuit reconstructurability because of manufacturing yield problems. In the hybrid wafer-scale integration (HWSI) approach, individual pre-tested chips are bonded to a fine-line interconnect structure fabricated on the surface of a wafer-scale substrate. With this technique, high yields can be achieved without redundancy.
- Research Organization:
- Space Computer Corp., Santa Monica, CA (USA)
- OSTI ID:
- 5521903
- Report Number(s):
- AD-A-209944/8/XAB; SCC-R-104-F
- Country of Publication:
- United States
- Language:
- English
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Related Subjects
99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
COMPUTER ARCHITECTURE
INFRARED THERMOGRAPHY
INTEGRATED CIRCUITS
CAPACITANCE
COMMUNICATIONS
ENERGY CONSUMPTION
MANUFACTURING
PACKAGING
PROGRESS REPORT
DOCUMENT TYPES
ELECTRICAL PROPERTIES
ELECTRONIC CIRCUITS
MEASURING METHODS
MICROELECTRONIC CIRCUITS
PHYSICAL PROPERTIES
THERMOGRAPHY
420800* - Engineering- Electronic Circuits & Devices- (-1989)
990200 - Mathematics & Computers