Interstitial fault tolerance-a technique for making systolic arrays fault tolerant

Conference · Sat Jan 01 00:00:00 EST 1983

OSTI ID:5257924

Kuhn, R H

Systolic arrays are a popular model for the implementation of highly parallel VLSI systems. In this paper interstitial fault tolerance (IFT), a technique for incorporating fault tolerance into systolic arrays in a natural manner, is discussed. IFT can be used for reliable computation or for yield enhancement. Previous fault tolerance techniques for reliable computation on SIMD systems have employed redundant hardware. IFT on the other hand employs time redundancy. Previous wafer scale integration techniques for yield enhancement have been proposed only for linear processing element arrays. Ift is effective for both linear and two dimensional arrays. The time redundancy to achieve IFT is shown to be bounded by a factor of 3, allowing no processor redundancy. Results of monte carlo simulation of ift are presented. 19 references.

• OSTI ID: 5257924
• Resource Relation: Conference: Sponsored by Hawaii international conference system science, Honolulu, HI, USA, 5 Jan 1983
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
ARRAY PROCESSORS
FAILURES
ARCHITECTURE
ELECTRONIC EQUIPMENT
INTEGRATED CIRCUITS
MONTE CARLO METHOD
PARALLEL PROCESSING
ELECTRONIC CIRCUITS
EQUIPMENT
MICROELECTRONIC CIRCUITS
PROGRAMMING
990200* - Mathematics & Computers