Efficient multiprocessor architecture for digital signal processing

Conference · Fri Jan 01 00:00:00 EST 1982

OSTI ID:5213943

Auguin, M; Boeri, F

There is a continuing pressure of better processing performances in numerical signal processing. Effective utilization of LSI semiconductor technology allows the consideration of multiprocessor architectures. The problem of interconnecting the components of the architecture arises. The authors describe a control algorithm of the Benes interconnection network in a asynchronous multiprocessor system. A simulation study of the time-shared bus, of the omega network, of the benes network and of the crossbar network gives a comparison of performances. 8 references.

• OSTI ID: 5213943
• Report Number(s): CONF-820520-
• Resource Relation: Conference: IEEE conference on acoustics, speech and signal processing, Paris, France, 3 May 1982
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
ARRAY PROCESSORS
PERFORMANCE
ALGORITHMS
ARCHITECTURE
DATA PROCESSING
IMAGE PROCESSING
SIGNALS
MATHEMATICAL LOGIC
PROCESSING
990200* - Mathematics & Computers