The EPSILON-2 hybrid dataflow architecture

Grafe, V. G.; Hoch, J. E.

doi:10.1109/CMPCON.1990.63658

Title: The EPSILON-2 hybrid dataflow architecture

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Abstract

EPSILON-2 is a general parallel computer architecture that combines the fine grain parallelism of dataflow computing with the sequential efficiency common to von Neumann computing. Instruction level synchronization, single cycle context switches, and RISC-like sequential efficiency are all supported in EPSILON-2. The general parallel computing model of EPSILON-2 is described, followed by a description of the processing element architecture. A sample code is presented in detail, and the progress of the physical implementation discussed. 11 refs., 14 figs.

Authors:: Grafe, V. G.; Hoch, J. E.

Publication Date:: Wed Nov 08 00:00:00 EST 1989

Research Org.:: Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

Sponsoring Org.:: DOE/DP

OSTI Identifier:: 5213672

Report Number(s):: SAND-89-2622C; CONF-900251-1
ON: DE90003152

DOE Contract Number:: AC04-76DP00789

Resource Type:: Conference

Resource Relation:: Conference: COMPCON '90, San Francisco, CA (USA), 27 Feb - 1 Mar 1990

Country of Publication:: United States

Language:: English

Subject:: 99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE; ARRAY PROCESSORS; COMPUTER ARCHITECTURE; DATA-FLOW PROCESSING; PARALLEL PROCESSING; PROGRAMMING; 990200* - Mathematics & Computers

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                    Grafe, V. G., and Hoch, J. E. The EPSILON-2 hybrid dataflow architecture.  United States: N. p., 1989. 
        Web.  doi:10.1109/CMPCON.1990.63658.

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                    Grafe, V. G., & Hoch, J. E. The EPSILON-2 hybrid dataflow architecture.  United States.  https://doi.org/10.1109/CMPCON.1990.63658

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                    Grafe, V. G., and Hoch, J. E. 1989.  
        "The EPSILON-2 hybrid dataflow architecture".  United States.  https://doi.org/10.1109/CMPCON.1990.63658.  https://www.osti.gov/servlets/purl/5213672.

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@article{osti_5213672,

  title        = {The EPSILON-2 hybrid dataflow architecture},

  author       = {Grafe, V. G. and Hoch, J. E.},

  abstractNote = {EPSILON-2 is a general parallel computer architecture that combines the fine grain parallelism of dataflow computing with the sequential efficiency common to von Neumann computing. Instruction level synchronization, single cycle context switches, and RISC-like sequential efficiency are all supported in EPSILON-2. The general parallel computing model of EPSILON-2 is described, followed by a description of the processing element architecture. A sample code is presented in detail, and the progress of the physical implementation discussed. 11 refs., 14 figs.},

  doi          = {10.1109/CMPCON.1990.63658},

  url          = {https://www.osti.gov/biblio/5213672},
  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {Wed Nov 08 00:00:00 EST 1989},

  month        = {Wed Nov 08 00:00:00 EST 1989}

}

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