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Title: Advanced digital processor technology base development for Navy applications: the S-1 project

Advanced digital processor technology base development for Navy applications: the S-1 project The design of a state-of-the-art, high-performance data processor is presented. A general description of the S-1 multiprocessor architecture and an overview of the organization of a specific S-1 multiprocessor configuration are given first. Then processor architecture is described in detail, including caches, virtual memory, memory access modes, status, I/O, and instruction set definition. The S-1 design system (SCALD) used to design and implement both single- and multiprocessor configuration is then discussed. Finally, the detailed design and hardware implementation of the first prototype S-1 processor are presented. 388 figures. (RWR)
Authors: ; ;
Publication Date:
OSTI Identifier:5106404
Report Number(s):UCID-17705
DOE Contract Number:W-7405-ENG-48
Resource Type:Technical Report
Data Type:
Research Org:California Univ., Livermore (USA). Lawrence Livermore Lab.
Country of Publication:United States
Language:English
Subject: 99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE; DIGITAL COMPUTERS; COMPUTER-AIDED DESIGN; DIAGRAMS; ELECTRONIC CIRCUITS; COMPUTERS 990200* -- Mathematics & Computers