A new approach towards accelerating VLSI - synthesis
- Univ. of Rostock (Germany)
In order to accelerate high-level synthesis and to improve the quality of synthesized circuits, new methods are needed which enable the use of the acceleration possibilities offered by parallel computing. Apart from the partitioning of (V)HDL models followed by distributed synthesis, even the three fundamental steps of high-level synthesis themselves (allocation, assignment and scheduling) can be objectives for acceleration. In contrast to most conventional synthesis applications which treat these steps more or less separately, the method discussed in this paper regards assignment and scheduling of high-level synthesis as a single process. The proposed method offers scheduling results at or near the optimum and can easily be used in a parallel computer.
- OSTI ID:
- 501615
- Report Number(s):
- CONF-961239-; TRN: 97:002723-0034
- Resource Relation:
- Conference: IDPT-2: 2. world conference on integrated design and process technology, Austin, TX (United States), 1-4 Dec 1996; Other Information: PBD: 1996; Related Information: Is Part Of Integrated design and process technology. Volume 1; Cooke, D.; Kraemer, B.J.; Sheu, P.C.Y.; Tsai, J.P.; Mittermeir, R. [eds.]; PB: 488 p.
- Country of Publication:
- United States
- Language:
- English
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