Laterally etched undercut (LEU) technique to reduce base-collector capcitances in heterojunction bipolar transistors
Conference
·
OSTI ID:405406
- and others
The authors report a novel fabrication process aimed at reducing the parasitic junction capacitance of AlGaAs/GaAs heterojunction bipolar transistors. The process, named as the Laterally Etched Undercut (LEU) process, physically removes the extrinsic base-collector junction area and results in a cantilever structure. The d.c., small-signal, and large-signal performances of the LEU devices are compared to those obtained from the conventional devices.
- OSTI ID:
- 405406
- Report Number(s):
- CONF-951097-; TRN: 96:004544-0047
- Resource Relation:
- Conference: IEEE gallium arsenide integrated circuits symposium: integrated circuits in GaAs, InP, and other compound semiconductors, San Diego, CA (United States), 29 Oct - 1 Nov 1995; Other Information: PBD: 1995; Related Information: Is Part Of GaAs IC symposium. Technical digest 1995; PB: 349 p.
- Country of Publication:
- United States
- Language:
- English
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