Enhanced CAD model for gate leakage current in heterostructure field effect transistors
- Chungbuk National Univ., Cheongju (Korea, Republic of). Dept. of Electronics Engineering
- Rogaland Research, Stavanger (Norway)
- Univ. of Virginia, Charlottesville, VA (United States). Dept. of Electrical Engineering
- Sandia National Labs., Albuquerque, NM (United States)
- Wright Lab., Wright-Patterson AFB, OH (United States). Solid State Technology Directorate
A simple and accurate circuit model for Heterostructure Field Effect Transistors (HFET`s) is proposed to simulate both the gate and the drain current characteristics accounting for hot-electron effects on gate current and the effect of the gate current on the channel current. An analytical equation that describes the effective electron temperature is developed in a simple form. This equation is suitable for implementation in circuit simulators. The model describes both the drain and gate currents at high gate bias voltages. It has been implemented in the circuit simulator AIM-Spice, and good agreement between simulated and measured results is achieved for enhancement-mode HFET`s fabricated in different laboratories. The proposed equivalent circuit and model equations are applicable to other compound semiconductor FET`s, i.e., GaAs MESFET`s.
- OSTI ID:
- 253655
- Journal Information:
- IEEE Transactions on Electron Devices, Vol. 43, Issue 6; Other Information: PBD: Jun 1996
- Country of Publication:
- United States
- Language:
- English
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