Elevated voltage level I{sub DDQ} failure testing of integrated circuits
Patent
·
OSTI ID:238071
Burn in testing of static CMOS IC`s is eliminated by I{sub DDQ} testing at elevated voltage levels. These voltage levels are at least 25% higher than the normal operating voltage for the IC but are below voltage levels that would cause damage to the chip. 4 figs.
- Research Organization:
- Sandia National Laboratories (SNL), Albuquerque, NM, and Livermore, CA (United States)
- DOE Contract Number:
- AC04-94AL85000
- Assignee:
- Sandia Corp., Albuquerque, NM (United States)
- Patent Number(s):
- US 5,519,333/A/
- Application Number:
- PAN: 8-303,849
- OSTI ID:
- 238071
- Resource Relation:
- Other Information: PBD: 21 May 1996
- Country of Publication:
- United States
- Language:
- English
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