Thermomechanical characterization and modeling for TSV structures
- Microelectronics Research Center, University of Texas, Austin, TX 78712 (United States)
- Department of Aerospace Engineering and Engineering Mechanics, University of Texas, Austin, TX 78712 (United States)
Continual scaling of devices and on-chip wiring has brought significant challenges for materials and processes beyond the 32-nm technology node in microelectronics. Recently, three-dimensional (3-D) integration with through-silicon vias (TSVs) has emerged as an effective solution to meet the future technology requirements. Among others, thermo-mechanical reliability is a key concern for the development of TSV structures used in die stacking as 3-D interconnects. This paper presents experimental measurements of the thermal stresses in TSV structures and analyses of interfacial reliability. The micro-Raman measurements were made to characterize the local distribution of the near-surface stresses in Si around TSVs. On the other hand, the precision wafer curvature technique was employed to measure the average stress and deformation in the TSV structures subject to thermal cycling. To understand the elastic and plastic behavior of TSVs, the microstructural evolution of the Cu vias was analyzed using focused ion beam (FIB) and electron backscattering diffraction (EBSD) techniques. Furthermore, the impact of thermal stresses on interfacial reliability of TSV structures was investigated by a shear-lag cohesive zone model that predicts the critical temperatures and critical via diameters.
- OSTI ID:
- 22311261
- Journal Information:
- AIP Conference Proceedings, Vol. 1601, Issue 1; Conference: International conference on stress induced phenomena and reliability in 3D microelectronics, Kyoto (Japan), 28-30 May 2012; Other Information: (c) 2014 AIP Publishing LLC; Country of input: International Atomic Energy Agency (IAEA); ISSN 0094-243X
- Country of Publication:
- United States
- Language:
- English
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