Low defect InGaAs quantum well selectively grown by metal organic chemical vapor deposition on Si(100) 300 mm wafers for next generation non planar devices
- Univ. Grenoble Alpes, LTM, F-38000 France CNRS, LTM, F-38000 Grenoble (France)
- Univ. Grenoble Alpes, F-38000, France CEA-LETI, MINATEC Campus, F-38054 Grenoble (France)
- Institut des Nanotechnologies de Lyon (INL)-UMR5270-CNRS, INSA-Lyon, Université de Lyon, 7 Avenue Jean Capelle, 69621 Villeurbanne (France)
- Applied Materials, 3050 Bowers Avenue, Santa Clara, California 95054 (United States)
Metal organic chemical vapor deposition of GaAs, InGaAs, and AlGaAs on nominal 300 mm Si(100) at temperatures below 550 °C was studied using the selective aspect ratio trapping method. We clearly show that growing directly GaAs on a flat Si surface in a SiO{sub 2} cavity with an aspect ratio as low as 1.3 is efficient to completely annihilate the anti-phase boundary domains. InGaAs quantum wells were grown on a GaAs buffer and exhibit room temperature micro-photoluminescence. Cathodoluminescence reveals the presence of dark spots which could be associated with the presence of emerging dislocation in a direction parallel to the cavity. The InGaAs layers obtained with no antiphase boundaries are perfect candidates for being integrated as channels in n-type metal oxide semiconductor field effect transistor (MOSFET), while the low temperatures used allow the co-integration of p-type MOSFET.
- OSTI ID:
- 22303890
- Journal Information:
- Applied Physics Letters, Vol. 104, Issue 26; Other Information: (c) 2014 AIP Publishing LLC; Country of input: International Atomic Energy Agency (IAEA); ISSN 0003-6951
- Country of Publication:
- United States
- Language:
- English
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Related Subjects
SUPERCONDUCTIVITY AND SUPERFLUIDITY
ALUMINIUM COMPOUNDS
ASPECT RATIO
BUFFERS
CATHODOLUMINESCENCE
CHEMICAL VAPOR DEPOSITION
DEFECTS
DISLOCATIONS
GALLIUM ARSENIDES
INDIUM COMPOUNDS
LAYERS
MOSFET
N-TYPE CONDUCTORS
ORGANOMETALLIC COMPOUNDS
PHOTOLUMINESCENCE
P-TYPE CONDUCTORS
QUANTUM WELLS
SILICON
SILICON OXIDES
SURFACES
TRAPPING