Plasma immersion ion implantation for sub-22 nm node devices: FD-SOI and Tri-Gate

Journal Article · Tue Nov 06 00:00:00 EST 2012 · AIP Conference Proceedings

DOI:https://doi.org/10.1063/1.4766492· OSTI ID:22075735

Duchaine, J; Milesi, F; Coquand, R; Barraud, S; Reboh, S; Gonzatti, F; Mazen, F; Torregrosa, Frank ^[1]

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1. IBS, ZI Peynier-Rousset, Avenue Gaston Imbert prolongee, 13 790 Peynier (France) and CEA, LETI, MINATEC Campus, 17 rue des Martyrs, 38054 GRENOBLE Cedex 9 (France)

Here, we present and discuss the electrical characteristics of fully depleted MOSFET transistors of planar and tridimensional architecture, doped by Plasma Immersion Ion Implantation (PIII) or Beam Line Ion Implantation (BLII). Both techniques delivered similar and satisfactory results in considering the planar architecture. For tri-dimensional Tri-Gate transistors, the results obtained with PIII are superior.

• OSTI ID: 22075735
• Journal Information: AIP Conference Proceedings, Vol. 1496, Issue 1; Conference: 19. international conference on ion implantation technology, Valladolid (Spain), 25-29 Jun 2012; Other Information: (c) 2012 American Institute of Physics; Country of input: International Atomic Energy Agency (IAEA); ISSN 0094-243X
• Country of Publication: United States
• Language: English

Related Subjects

36 MATERIALS SCIENCE
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY
70 PLASMA PHYSICS AND FUSION TECHNOLOGY
DOPED MATERIALS
ION BEAMS
ION IMPLANTATION
MOSFET
PLASMA
SEMICONDUCTOR MATERIALS
SILICON