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Title: Room temperature Si {delta}-growth on Ge incorporating high-K dielectric for metal oxide semiconductor applications

Journal Article · · Applied Physics Letters
DOI:https://doi.org/10.1063/1.2957476· OSTI ID:21123978
; ;  [1]; ;  [2]; ;  [3]
  1. Department of Electrical Engineering, University of California Los Angeles, Los Angeles, California 90095 (United States)
  2. School of Engineering and Centre for Microscopy and Microanalysis, The University of Queensland, Brisbane, St Lucia, Queensland 4072 (Australia)
  3. Department of Materials Science and Engineering, University of California Los Angeles, Los Angeles, California 90095 (United States)

A low temperature Al{sub 2}O{sub 3}/4 monolayer amorphous Si gate stack process was demonstrated on p-type Ge wafers using atomic layer deposition and molecular beam epitaxy. Multifrequency capacitance-voltage (C-V) and current-voltage (I-V) characteristics showed excellent electrical properties of the Pt/Al{sub 2}O{sub 3}/4 ML Si/Ge metal oxide semiconductor capacitor. No kinks from 1 MHz to 4 kHz and a leakage current density of 2.6x10{sup -6} A/cm{sup 2} at 1 V with an equivalent oxide thickness of 2.5 nm. The interface characterization using a conductance method showed that interface trap density at the near midgap was 8x10{sup 12} eV{sup -1} cm{sup -2} and a mean capture cross section of holes was extracted to be 10{sup -16} cm{sup 2}.

OSTI ID:
21123978
Journal Information:
Applied Physics Letters, Vol. 93, Issue 2; Other Information: DOI: 10.1063/1.2957476; (c) 2008 American Institute of Physics; Country of input: International Atomic Energy Agency (IAEA); ISSN 0003-6951
Country of Publication:
United States
Language:
English