Interface trap and oxide charge generation under negative bias temperature instability of p-channel metal-oxide-semiconductor field-effect transistors with ultrathin plasma-nitrided SiON gate dielectrics
- Research Center for Nanodevices and Systems, Hiroshima University, 1-4-2 Kagamiyama, Higashi-Hiroshima 739-8527 (Japan)
The interface trap generation ({delta}N{sub it}) and fixed oxide charge buildup ({delta}N{sub ot}) under negative bias temperature instability (NBTI) of p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) with ultrathin (2 nm) plasma-nitrided SiON gate dielectrics were studied using a modified direct-current-current-voltage method and a conventional subthreshold characteristic measurement. Different stress time dependences were shown for {delta}N{sub it} and {delta}N{sub ot}. At the earlier stress times, {delta}N{sub it} dominates the threshold voltage shift ({delta}V{sub th}) and {delta}N{sub ot} is negligible. With increasing stress time, the rate of increase of {delta}N{sub it} decreases continuously, showing a saturating trend for longer stress times, while {delta}N{sub ot} still has a power-law dependence on stress time so that the relative contribution of {delta}N{sub ot} increases. The thermal activation energy of {delta}N{sub it} and the NBTI lifetime of pMOSFETs, compared at a given stress voltage, are independent of the peak nitrogen concentration of the SiON film. This indicates that plasma nitridation is a more reliable method for incorporating nitrogen in the gate oxide.
- OSTI ID:
- 20714164
- Journal Information:
- Journal of Applied Physics, Vol. 98, Issue 11; Other Information: DOI: 10.1063/1.2138372; (c) 2005 American Institute of Physics; Country of input: International Atomic Energy Agency (IAEA); ISSN 0021-8979
- Country of Publication:
- United States
- Language:
- English
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