Chip-Level Electromigration Reliability for Cu Interconnects
- Technology Solutions Organization, Freescale Semiconductor (United States)
- Sector Quality, Freescale Semiconductor (United States)
Even after the successful introduction of Cu-based metallization, the electromigration (EM) failure risk has remained one of the most important reliability concerns for most advanced process technologies. Ever increasing operating current densities and the introduction of low-k materials in the backend process scheme are some of the issues that threaten reliable, long-term operation at elevated temperatures. The traditional method of verifying EM reliability only through current density limit checks is proving to be inadequate in general, or quite expensive at the best. A Statistical EM Budgeting (SEB) methodology has been proposed to assess more realistic chip-level EM reliability from the complex statistical distribution of currents in a chip. To be valuable, this approach requires accurate estimation of currents for all interconnect segments in a chip. However, no efficient technique to manage the complexity of such a task for very large chip designs is known. We present an efficient method to estimate currents exhaustively for all interconnects in a chip. The proposed method uses pre-characterization of cells and macros, and steps to identify and filter out symmetrically bi-directional interconnects. We illustrate the strength of the proposed approach using a high-performance microprocessor design for embedded applications as a case study.
- OSTI ID:
- 20630486
- Journal Information:
- AIP Conference Proceedings, Vol. 741, Issue 1; Conference: 7. international workshop on stress-induced phenomena in metallization, Austin, TX (United States), 14-16 Jun 2004; Other Information: DOI: 10.1063/1.1845838; (c) 2004 American Institute of Physics; Country of input: International Atomic Energy Agency (IAEA); ISSN 0094-243X
- Country of Publication:
- United States
- Language:
- English
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