An SEU analysis approach for error propagation in digital VLSI CMOS ASICs
- Boeing Defense and Space Group, Seattle, WA (United States)
- SFA Inc., Landover, MD (United States)
A critical issue in the development of ASIC designs is the ability to achieve first pass fabrication success. Unsuccessful fabrication runs have serious impact on ASIC costs and schedules. The ability to predict an ASICs radiation response prior to fabrication is therefore a key issue when designing ASICs for military and aerospace systems. This paper describes an analysis approach for calculating static bit error propagation in synchronous VLSI CMOS circuits developed as an aid for predicting the SEU response of ASIC`s. The technique is intended for eventual application as an ASIC development simulation tool which can be used by circuit design engineers for performance evaluation during the pre-fabrication design process in much the same way that logic and timing simulators are used.
- OSTI ID:
- 203709
- Report Number(s):
- CONF-950716-; ISSN 0018-9499; TRN: 96:009673
- Journal Information:
- IEEE Transactions on Nuclear Science, Vol. 42, Issue 6Pt1; Conference: 32. annual IEEE international nuclear and space radiation effects conference, Madison, WI (United States), 17-21 Jul 1995; Other Information: PBD: Dec 1995
- Country of Publication:
- United States
- Language:
- English
Similar Records
Design and implementation of moment invariants for pattern recognition in VLSI (very large scale integration)
Single event upset test structures for digital CMOS application specific integrated circuits