Application of high pressure deuterium annealing for improving the hot carrier reliability of CMOS transistors
The authors present the effect of high pressure deuterium annealing on hot carrier reliability improvements of CMOS transistors. High pressure annealing increases the rate of deuterium incorporation at the SiO{sub 2}/Si interface. They have achieved a significant lifetime improvement (90 {times}) from fully processed wafers (four metal layers) with nitride sidewall spacers and SiON cap layers. The improvement was determined by comparing to wafers that were annealed in a conventional hydrogen forming gas anneal. The annealing time to achieve the same level of improvement is also significantly reduced. The increased incorporation of D at high pressure was confirmed by the secondary ion mass spectrometry characterization.
- Research Organization:
- Univ. of Illinois, Urbana, IL (US)
- Sponsoring Organization:
- USDOE
- OSTI ID:
- 20067760
- Journal Information:
- IEEE Electron Device Letters (Institute of Electrical and Electronics Engineers), Vol. 21, Issue 5; Other Information: PBD: May 2000; ISSN 0741-3106
- Country of Publication:
- United States
- Language:
- English
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