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Title: Memory hierarchy using row-based compression

A system includes a first memory and a device coupleable to the first memory. The device includes a second memory to cache data from the first memory. The second memory includes a plurality of rows, each row including a corresponding set of compressed data blocks of non-uniform sizes and a corresponding set of tag blocks. Each tag block represents a corresponding compressed data block of the row. The device further includes decompression logic to decompress data blocks accessed from the second memory. The device further includes compression logic to compress data blocks to be stored in the second memory.
Authors:
;
Publication Date:
OSTI Identifier:
1330324
Report Number(s):
9,477,605
13/939,377
DOE Contract Number:
AC52-07NA27344
Resource Type:
Patent
Resource Relation:
Patent File Date: 2013 Jul 11
Research Org:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING